1. Field of the Invention
This invention relates to a method for fabricating semiconductor devices, and more particularly, to a self-aligned method for simultaneously forming bit-line contacts and node contacts.
2. Description of Related Art
FIG. 1A is a top view of the bit-line contacts and node contacts formed by a conventional fabricating method. FIG. 1B is a cross-sectional view of the I-I' plane showing the structure shown in FIG. 1A.
Bit-line contacts and node contacts are formed conventionally. In FIG. 1A, the entire structure is covered by a dielectric layer (not shown). The structure includes patterned polysilicon layer 102, bit line 104, and nodes 105. The bit line 104 is electrically connected to the substrate underneath through a bit-line contact, and the nodes 105 are electrically connected the substrate underneath through node contacts. Area 108 is the patterned to form the bit-line contact, and areas 106 are patterned to form the node contacts.
FIG. 1B is a cross-sectional view showing the structure as seen from plane 1, in which the substrate includes an isolation area 110 and an active area 112. The structure also includes a patterned polysilicon layer 102, spacers 114, which are formed on the sides of the polysilicon layer 102, and an insulator 116. Conventionally, a photoresist layer 118 is formed on the substrate and individually patterned into the pattern of the bit-line contact 108 and the patterns of the node contacts 106, as shown in FIG. 1A. The bit-line contact 108' and the node contacts 106' are formed by performing photolithography processes on the patterned photoresist layer 118.
Since the bit-line contact 108' and the node contacts 106' are individual openings, the formation of contacts is limited by the photolithography resolution as the dimension of devices is downsized. Because the separation between contact openings has to be wider than 0.22 .mu.m, the dimensions of contact openings cannot exceed a certain size. Furthermore, the separated contact openings increase the complication of the fabrication process, so the occurrence of alignment errors is increased as well. Moreover, the limitation on the contact dimensions makes the photolithographic windows of bit lines and nodes small, so the difficulties of the fabrication process increase.